Philip A Covington’s Blog

QS1R Software Defined Receiver: (Click on picture above for larger version.) Features: 16 bit 130 MSPS ADC HPF, LPF, RF AMP Switchable Front End 0-31.5 dB Attenuator in 0.5 dB steps Cyclone II FPGA Two AD6620 DDC co-processors USB 2.0 480 Mbps High Speed Interface to PC 0.1 to 33 MHz coverage (0.1 to 65 MHz extended) RX bandwidths from 33 MHz to 1kHz Two independent RX channels anywhere in 0.1 to 33 MHz 6.00" X 4.00" board size Single +12V 1A supply Open Source Software and Hardware Availability: Projected late January to mid-February 2007

vSound Status I have been able to get a prototype of the vSound driver to work on Windows Vista beta. I am now waiting until the official release of Vista to continue development on a driver that will work on both XP and Vista. As it looks now, vSound will support Vista and XP only. There will be no support for W2K, NT4, or Win9X/ME operating systems. My main concern is trying to make sure that the vSound driver is compatible with both XP and Vista so I don't have to maintain two different versions based on operating system. There are a lot of changes being made to driver development under Windows and I have been waiting until it stabilizes a little bit more before releasing a beta driver. My best estimate for availability of vSound beta is early next year after Vista systems hit the streets. New QuickSilver QS1R Group Support and discussion group for the new QuickSilver QS1R SDR: To sign up go Here

Links DSPLINKS - great for learning DSP interactively QUCS - circuit simulator for Linux and Windows LTC SWCAD - circuit simulator for Windows Cell Processor - the processor that power the PS3 SciLab - open source numerical computation Maxima - open source computer algebra system Octave - open source GNU numerical computation Mono - open source .NET Coming Soon! QuickSilver QS1R SDR Receiver/Scope/Spectrum Analyzer Board Based on Linear Technology LTC2208 130 MSPS 16 bit ADC Cyclone II EP2C8 FPGA for DDC processor High Speed USB 2.0 Connectivity Two DDC Co-processors External Clocking capability 6.00" x 4.00" (15.24 x 10.16 cm) board size 0.1-65 MHz Open Source Software

Here is a diagram of a SDR that uses ideas from the K2 RF front end and PLL synthesizer: K2LikeSDR.pdf It would use the K2's RF front end. I would substitute the TUF-1 mixer of the K2 with a switching mixer based on a FST3125 bus switch. The QSD would be at a fixed IF of 5 MHz. The LO for the QSD would be derived from a fixed 20 MHz oscillator divided by 4 to generate the quadrature signals needed to driver the QSD switches. The K2's PLL would be modified by eliminating the variable reference oscillator (resulting in the PLL tuning in 5 kHz steps) and substituting one of the LMX National PLLs for the MC145170 PLL used in the K2 design. The K2's VCO design is good, but I would also eliminate the VCO AGC circuit of the K2.

SDR LO Ideas: There has been a lot of discussion of using DDS or PLLs for the LO generation for HPSDR and SoftRock like receivers. In the current SoftRock series the LO is generated by a crystal oscillator. The downsides of the above approaches are: 1. DDS: spurs and cost of a decent low jitter/low noise clock source. Some of the 400 and 500 MHz DDS chips are on the expensive side. 2. PLL: phase noise. A scheme using a microwave VCO/PLL and dividing it down into the HF range has been discussed. The latest feeling is that the phase noise reduction even after dividing down is not enough to provide a high performance system. A dual PLL loop approach has been proposed to improve phase noise performance but it is likely to be expensive. There are also PLL/DDS approaches of varying complexity. 3. Xtal: limited frequency agility, you are limited to tuning within the passband of your computer sound card. There is a forth method that might work for lower cost SDR circuits like the SoftR

QSD/ISD Switches: Here is a link the PDF data sheets of analog switches that can be investigated for use in QSD/ISD circuits: http://www.philcovington.com/HPSDR/QSD_SWITCH/ Interesting ADC: Here is a link to an interesting ADC by Analog Devices: http://www.analog.com/UploadedFiles/Data_Sheets/AD7760.pdf It is a 24 bit, 2.5 MSPS ADC. Here is the circuit idea: http://www.philcovington.com/HPSDR/TEMP_STUFF/AD7760QSD.pdf It uses 1/2 of a QSD (not quadrature sampled) to mix the frequency band of interest down to zero Hz with a bandwidth of something like 250 kHz. The IF would be offset to something like 125 kHz. The ADC samples the 1/2QSD output and results in a real data stream. A FPGA or CPLD mixes the real data stream with a complex NCO to generate a quadrature data stream which is sent over USB to the PC where the remaining processing is done. The advantage is a 1 X LO and no I/Q balance problems. One disadvantage is that your sampling rate should be 4 times the desired bandwidth

vSOUND I thought I'd better post an update to my progress on the vSound virtual sound card driver. I have been looking at the WDF stuff from Microsoft and how it could be supported in the upcoming Vista. There are some considerable issues in writing sound drivers that will work in Vista with the Digital Rights Management (DRM) crap. I am hoping to write the driver so it will work in W2K, XP, and Vista. I would very much like for the driver to work like jack does in Linux. Some things are not possible in Windows, but I think I can get close to jack's functionality. I hope to have something together to test in a month or so. HPSDR OZY I posted a photo of a almost complete OZY board on the HPSDR Wiki . Testing is going well. See updated info at hpsdr.org 73 de Phil N8VB

http://www.arrl.org/news/features/2006/06/09/1/?nc=1 The other news is that HPSDR has joined forces with TAPR to provide bare boards and parts: http://www.tapr.org/kits_atlas.html?PHPSESSID=0e5e57933bb81af7e79b13ca6708d075

The HPSDR project is progressing nicely. We have a design for the ATLAS backplane that has passed the alpha stage. The JANUS board is close to alpha. The OZY board's schematic has been posted for review and comment. ATLAS orders are close to 200 boards now. If you have no idea what I am talking about check out: hpsdr.org Also join the HPSDR mail reflector which is quite active. www.hamsdr.com is another site you should check out if you are interested in Software Defined Radio.

HPSDR PROJECT: We have combined the HPSDR and XYLO SDR groups into one project with common goals. There is a new domain and website for the project: http://hpsdr.org The XYLO SDR mailing list has now become the HPSDR mailing list. To join the list go to: http://hpsdr.org/reflector.html ATLAS BUS: This is the first attempt at defining the physical layout of the Atlas bus. The board ended up being 5.500" x 3.940", six slots, and 4 layers with the following stackup: 1. Ground Plane (top component side) 2. YBUS 3. Power Plane (+12,-12, +5, -5, +3.3) 4. XBUS (bottom side) Details are in the following document: http://www.philcovington.com/HPSDR/ATLAS/Atlas_doc.pdf After reading the document there are some other pdfs (such as the schematic) in this folder: http://www.philcovington.com/HPSDR/ATLAS/ For those interested, I'd appreciate if you'd please take a look at the documents and make questions/comments.

LTC2208 Mercury Board: The HPSDR project is now broken down into various sub-projects. The most important is the Mercury board which contains the LTC2208 130 MSPS ADC. The Mercury board will also contain a FPGA to do the DDC (Digital Down Conversion) function. There will probably be an option to install a Cypress FX2 USB2 microcontroller to make the board stand alone for certain applications. Otherwise the FPGA will connect to the Atlas bus. If you are not sure what Atlas is then see the Xylo list archives. I have a few LTC 2208 evaluation boards coming from Linear Technology. They should arrive this week. I want to compare the LVDS board to the CMOS board to see if there are any advantages of using the LVDS mode for the 1-70 MHz range. Initially I think I will program the on board FPGA so that the 130 MSPS from the LTC2208 are downsampled to <= 250 kSPS. The 250kSPS then can be processed in the same way that we process the data from the soundcard. PowerSDR can then be modi

I have settled on the Linear Technology LTC2208 16 bit, 130 MSPS ADC for the HPSDR project. The LTC2208 has some unique features that put it ahead of offerings from Analog Devices. Here is the datasheet: http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1155,C1001,C1150,P13693,D9659 of particular interest is the PGA, randomizer and dithering features. We completed our move into our new home last weekend. We are getting settled in and soon I will start on the Mercury board - which is based on the LTC2208.