Skip to main content

vSound Update

vSound Status

I have been able to get a prototype of the vSound driver to work on Windows Vista beta. I am now waiting until the official release of Vista to continue development on a driver that will work on both XP and Vista. As it looks now, vSound will support Vista and XP only. There will be no support for W2K, NT4, or Win9X/ME operating systems. My main concern is trying to make sure that the vSound driver is compatible with both XP and Vista so I don't have to maintain two different versions based on operating system.

There are a lot of changes being made to driver development under Windows and I have been waiting until it stabilizes a little bit more before releasing a beta driver. My best estimate for availability of vSound beta is early next year after Vista systems hit the streets.

New QuickSilver QS1R Group

Support and discussion group for the new QuickSilver QS1R SDR:


To sign up go Here

Comments

Popular posts from this blog

History of HPSDR Mercury and Quick Silver

History of HPSDR Mercury and Quick Silver Philip Covington, N8VB Early HPSDR and XYLO In 2005 I started a High Performance SDR (HPSDR) project which was to consist of a motherboard carrying a FPGA/USB 2.0 interface and power supply with the provision for plug in modules through 40 pin headers. I had planned a narrow band high dynamic range module based on a QSD/DDS/PCM4202 audio ADC and a wide bandwidth module based on a high speed 16 bit ADC: http://www.philcovington.com/SDR/PICS/HPSDR_FPGA_USB_Board_top1_800600.jpg http://www.philcovington.com/SDR/PICS/HPSDR_FPGA_USB_Board_top4.jpg I soon selected the LTC2208 ADC from Linear Technology. A representative from Linear Technology came across my blog ( http://pcovington.blogspot.com/ ) and offered evaluation boards and samples to support the project. At about the same time my HPSDR project came about, Phil Harman, VK6APH and Bill Tracey, KD5TFD were interested developing a sound card replacement to be used with the SD

QuickSilver QS1R Software Defined Receiver Prototype

QS1R Software Defined Receiver: (Click on picture above for larger version.) Features: 16 bit 130 MSPS ADC HPF, LPF, RF AMP Switchable Front End 0-31.5 dB Attenuator in 0.5 dB steps Cyclone II FPGA Two AD6620 DDC co-processors USB 2.0 480 Mbps High Speed Interface to PC 0.1 to 33 MHz coverage (0.1 to 65 MHz extended) RX bandwidths from 33 MHz to 1kHz Two independent RX channels anywhere in 0.1 to 33 MHz 6.00" X 4.00" board size Single +12V 1A supply Open Source Software and Hardware Availability: Projected late January to mid-February 2007

2323 Wilt